The Implementation of a Reliable Router Chip
نویسندگان
چکیده
This thesis describes the implementation of a router chip for a network of processors. The router features the simultaneous bidirection pad drivers and a diagnostic port with a JTAG interface. The design process results in some useful experience for the development of a complex VLSI system in an academic research environment. The router chip is designed for a 3.3v 0.8pm 3 metal layers CMOS process, and is targeted to run at 100MHz. Thesis Supervisor: William J. Dally Title: Associate Professor
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